Because of their small size, low cost, ease of use and digital output, integrated temperature sensors are widely used. These integrated temperature sensors are often based on the temperature dependence of bipolar transistors (BJTs). However, because BJTs are sensitive to process spread, their untrimmed inaccuracy is typically limited to a few degrees Celsius. While the inaccuracy of BJTs can be improved by trimming individual devices, this usually increases production test time and the device cost. Furthermore, in advanced deep-submicron CMOS technologies (such as those used in state-of-the-art microprocessors), the performance of BJT-based temperature sensors usually deteriorates significantly. For example, temperature errors of up to 5° C. have been reported. This degraded performance is at odds with the increasing need for thermal management (and for integrated temperature sensors) in microprocessors and other very-large-scale integrated circuits (ICs) because of the increasing power density and the increasing number of processing cores in such chips.
Another technique for measuring temperature (T) is via the thermal diffusivity of silicon (D), which has a T1.8 temperature dependence. For example, D can be determined by measuring the characteristics of an electrothermal filter (ETF). As shown in FIG. 1, an existing ETF can include a heater and a relative temperature sensor (such as a thermopile) fabricated on the substrate of a silicon chip. In the ETF, power dissipated in the heater generates heat pulses that diffuse through the silicon over a distance (s) between the heater and the temperature sensor, creating temperature fluctuations at the temperature sensor. The time it takes for these pulses to diffuse is a function of absolute temperature or, in other words, the ETF adds a temperature-dependent phase shift (φETF) to a signal at a particular frequency. When the heater is driven at a frequency (fdrive), the temperature sensor output has the same frequency but with a relative phase shift that can be approximated as
      ϕ    ETF    ∝            -      s        ⁢                                        π            ⁢                                                  ⁢                          f              drive                                D                    .      At constant fdrive, φETF has a near-linear T0.9 temperature dependence. Therefore, by digitizing the time delay associated with diffusion of the heat pulses, ETFs can be used as temperature sensors. Note that microprocessors typically operate at well-defined clock frequencies, so that a known fdrive is usually available in these applications.
In contrast to BJTs, ETFs usually do not require trimming because, for IC-grade silicon, D is well-defined and the distance between the heater and the relative temperature sensor is typically accurately determined by lithography. As a consequence, the inaccuracy of an ETF-based temperature sensor scales with the critical dimension of the lithographic process used. For example, ETFs with identical geometry have achieved untrimmed inaccuracies of ±0.7° C. (3σ) and ±0.2° C. (3σ) in 0.7 μm and 0.18 μm CMOS, respectively, indicating that the dominant source of error is lithographic spread. Therefore, the performance of ETFs is expected to improve greatly in modern microprocessors, which are implemented in even more advanced deep-submicron CMOS processes. Furthermore, because D is only weakly sensitive to doping fluctuations at the doping levels typically used in IC technology, the variation between wafers and process lots is small.
The availability of a known driving frequency together with the scaling properties of ETFs make them a promising alternative to current thermal management solutions in modern microprocessors. However, because of power-consumption constraints, the amount of power dissipated in the heater of an ETF is typically limited. In conjunction with the high thermal conductivity of silicon, this power-dissipation constraint leads to small signals at the output of the temperature sensor. Therefore, a precision readout interface is usually needed to extract φETF (and, thus, temperature information) from these small signals.
FIG. 2 illustrates an existing system that includes a phase-detection circuit. In this circuit, the ETF is driven at a constant frequency fdrive (which may be obtained from a digital system clock), and its phase-shifted output is multiplied with a reference signal at the same frequency but having a controlled phase shift (φdemod). Furthermore, the DC component of the multiplier output is proportional to the cosine of φdemod−φETF. The integrator in the phase-detection circuit in FIG. 2 drives the phase-shift controller so that this DC component becomes zero, which corresponds to a fixed 90° difference between the two phase shifts. As a consequence, this feedback loop functions as a narrowband and, therefore, low-noise, phase detector. While FIG. 2 includes a sine-wave drive, fdrive can be associated with an arbitrary periodic signal. For example, a square-wave may be used. Note that, because the ETF is a low-pass filter, the amplitude of the higher harmonics of fdrive in its output signal will be quite small.
When the feedback loop in the phase-detection circuit is locked, the analog control signal driving the phase shifter is a measure for φETF. However, the processing of the signals output by the ETF typically requires them to be digital, and so a phase-domain analog-to-digital converter (ADC) is often used. Such an ADC digitizes the relative phase difference between two signals, both of which are at the same frequency.
As shown in FIG. 3, one way to implement a phase-domain ADC is to replace the analog-controlled phase shifter with a digital one. In this circuit, an n-bit ADC samples the integrator output at a sampling rate fsample (which may be oversampled for high resolution), and feedback is provided through an n-bit digital phase rotator. However, for high n (for example, more than 12 bits), the implementation of an accurate digital phase rotator or an n-bit ADC is usually non-trivial. Typically, a single-bit phase-domain delta-sigma ADC (PDΔΣ) is easier to implement.
An existing system that includes a single-bit PDΔΣ ADC is illustrated in FIG. 4. This PDΔΣ ADC is a 1-bit implementation of the phase-detection circuit shown in FIG. 3. The two phase shift references, φ0 and φ1, are digitally generated square-waves with the same frequency as the input signal and which span the phase-shift input range of interest (for clarity, the fundamental harmonics are indicated in FIG. 4). Moreover, the value of fsample is chosen to be substantially larger than the signal bandwidth, which is referred to as ‘oversampling.’ In such an oversampled modulator (which is often referred to as a ‘delta-sigma modulator’), the quantization error associated with the 1-bit ADC is shifted out of the frequency band of interest through noise shaping, thereby offering high resolution after filtering by an appropriate decimation filter. The digital value obtained at the output of the decimation filter is thus a weighted average of the value of the input signal over the conversion period, and so such delta-sigma ADCs belong to the class of averaging converters. Delta-sigma ADCs are well suited for digitizing narrowband signals with high resolution, as is typically required for sensor interfacing. PDΔΣ ADCs have been successfully used to read out ETFs, achieving effective phase resolutions of up to 16 bits.
Usually, the phase-shift input range of the PDΔΣ ADC is chosen large enough to span the expected range of values for φETF over temperature. For example, φ0 and φ1 may be −45° and +45°, respectively, so that, as φETF varies from 60° to 100°, the cosine of φETF−φ0−90 is always positive, while the cosine of φETF−φ1−90 is always negative. This design choice ensures stable feedback-loop operation. FIG. 5 illustrates the measured ETF phase characteristic.
In many existing phase-domain ADCs there are typically non-idealities associated with the analog implementation of the integrator (loop filter) and the modulator. In particular, an analog integrator has several non-idealities, such as: limited dynamic range, non-linearity and finite DC gain. Moreover, the non-ideal switches used in analog demodulators can introduce charge injection and residual offset. It is increasingly difficult to design such analog circuits in modern nanometer-scale CMOS processes, which are basically optimized for the realization of digital circuits. The main challenges include the low intrinsic gain of the transistors (which often requires the use of complicated multi-stage amplifiers) and the low supply voltages (which reduce dynamic range and signal-to-noise ratio). Consequently, it is increasingly difficult to scale such readout architectures to the nanometer-scale CMOS processes in which large-scale integrated circuits (such as microprocessors) are realized.
Therefore, there is a need for a phase digitizer without the problems listed above.